With the rapid development of ultra large scale integration (ULSI), the fabrication process of integrate circuits (ICs) has become more and more complex; and more and more precise. In order to increase the integration level and lower the production cost, the number of the devices in a unit area has been increasing. Thus, it has been difficult to lay out lines (interconnect structure, etc) in one plane, i.e., two-dimensional layout; and a multiple-layered layout technique has been adapted to utilize the vertical space of the chip (three-dimensional) to further increase the integration level of devices. However, the multiple-layered layout technique may cause the surface of the silicon wafer to be uneven, and it may deteriorate the formation of the patterns, such as devices, and structures, etc. Therefore, in order to achieve the multi-layered layout on a wafer with a relatively large diameter, it may need to obtain an acceptable macroscopic levelness for each layer. That is, the conductors, interlayer dielectric (ILD) layers, metal, silicon oxide and nitrate of the multiple-layered interconnect structures may need to be planarized.
Currently, the chemical mechanical planarization (CMP) process may be a dominant method to achieve the acceptable macroscopic levelness for each layer of the chip. Especially when the semiconductor process enters into the sub-micron regime, the CMP process has become a major process of semiconductor manufacturing. The CMP process utilizes the relative motion between a wafer and a polishing platen to planarize (polishing) the surface of the wafer and/or devices, etc. Further, the CMP process utilizes the combination of chemical force and mechanical forces to achieve the planarization.
FIG. 1 illustrates an existing CMP apparatus.
As shown in FIG. 1, the CMP apparatus includes a platen 100, a polishing pad 102 covering on the platen 100. The CMP apparatus also includes a polishing head 104 configured to clamp a to-be-polished wafer 103; and a clamping fixture 105 configured to carry the polishing head 104 to rotate. Further, the CMP apparatus includes a polishing slurry supply tube 106 configured to provide a polishing slurry for a CMP process.
During the CMP process, the to-be-polished wafer 103 is attached on the polishing head 104. The to-be-polished surface of the wafer 103 faces downwardly; and is pressed by the polishing head 104 to attach on the surface of the polishing pad 102. When the platen 100 is rotated by an electrical motor, the polishing head 104 is also rotated by the clamping fixture 105 with a same direction as the platen 100. At the same time, a polishing slurry 107 is transferred onto the polishing pad 102 by the polishing slurry supply tube 106. With the combinational functions of the polishing head 104, the polishing pad 102 and the platen 100, the polishing slurry 107 are uniformly distributed on the polishing pad 102. During the CMP process, the polishing slurry 107 flows away from the edge of the polishing pad 102 under the centrifuge force.
However, during the CMP process, the CMP apparatus may scratch the to-be-polished wafer; thus it may need further improvements on the performance of the existing CMP apparatus. The disclosed device structures, methods and systems are directed to solve one or more problems set forth above and other problems.